1. Field of the Invention
The present invention relates to a memory device and method of operating such a memory device, and in particular to techniques for reducing the size of the access control circuitry required to read data from, and write data to, the memory device.
2. Description of the Prior Art
A typical memory device will have an array of memory cells arranged in a plurality of rows and a plurality of columns, and access control circuitry will be provided in association with the memory array to enable individual memory cells within the array to be accessed for the purposes of writing data to that memory cell or reading data from that memory cell.
FIG. 1 is a diagram schematically illustrating a typical array of memory cells, and further indicating the access control circuitry provided to access columns within the memory array. In particular, FIG. 1 shows an array of memory cells 10, 20, 30, 40, 50, 60 provided in association with a particular column multiplexer 70 of the memory device. Each row is addressed by a word line 16, 18, and each column has a pair of bit lines 12, 14, 22, 24, 32, 34 associated therewith. From an address provided to the memory device, a row and column within the memory device is identified, with the addressed memory cell being the memory cell at the intersection between the identified row and column. For a read operation, the word line 16, 18 associated with the selected row is selected in order to activate a row of cells, and then the column multiplexer 70 outputs to the IO (Input/Output) control block 80 an indication of the voltages on the pair of bit lines associated with the selected column, this indication identifying the value stored in the addressed memory cell. For a write operation, the word line is activated in the same manner, and the voltage on one of the pair of bit lines associated with the selected column is then discharged to identify the data value to be stored in the addressed memory cell.
As will be appreciated by those skilled in the art, various circuits are provided within the IO control block 80, including the write transistors required to discharge the voltage on one of the pair of bit lines to a logic zero value during a write operation, sense amplifier circuitry for detecting the value stored in the addressed memory cell from the voltage indications output by the column multiplexer 70, etc. It is also known in some implementations to include the sense amplifier circuitry between the bit lines and the column multiplexer, so that the column multiplexer 70 directly samples the output from the relevant sense amplifier.
Typically each memory cell stores a single bit data value, and accordingly if the data being accessed is a multi-bit data word (e.g. 32 bits, 64 bits, etc), it will be necessary to access multiple memory cells. In a typical design, column multiplexers will be provided corresponding to each bit of the data word, each column multiplexer being connected to the bit lines for a plurality of columns containing memory cells in which the associated bit of the data word can be stored. The memory array can hence be considered to be formed of a plurality of sections, one for each column multiplexer. Hence, by way of example a memory array may have 512 word lines, a multiplexer size of four (meaning four columns are connected to each column multiplexer), and a data word size of 32 bits (meaning there are 32 column multiplexers, each column multiplexer being connected to a corresponding section of the memory array). Such a memory can hence store 2048 32-bit data words.
The circuitry provided within the column multiplexers can take a variety of forms. In one known prior art technique, the write and read paths are maintained separately, with separate read pass gates and write pass gates connected to each bit line. Considering the example of FIG. 1 where there are two bit lines per column, this means that there will be four pass gate transistors per column, typically two NMOS transistors and two PMOS transistors. Separate control lines are required for the NMOS and PMOS transistors, and accordingly this will result in four transistors per column and two control lines per column.
Another alternative approach as shown in FIG. 2 is for the read and write paths to be combined, with a transfer gate 72, 74, 76, 78 being associated with each bit line. As shown in FIG. 2, each transfer gate comprises a PMOS transistor and an NMOS transistor coupled back to back, and again separate control signals are required for the PMOS and NMOS transistors. By forming transfer gates in this form, it can be ensured that during a read operation a voltage value at an input to the transfer gate will be propagated on from the output unchanged, irrespective of whether that voltage value represents a logic one level or a logic zero level. If only a single transistor is used on the read path, then for one possible voltage level the voltage level will be propagated on unchanged, whilst for the other possible voltage level the output will be changed due to the threshold voltage of the transistor. For example, if a single NMOS transistor were used as a pass gate for the read path, then a voltage level of zero will be propagated unchanged, but a voltage level of Vdd will be reduced to Vdd-Vth at the NMOS transistor's output, where Vth represents the threshold voltage of the NMOS transistor.
Whilst the transfer gate arrangement shown in FIG. 2 works well, it will be seen that it again requires two transistors per bit line, and accordingly for the arrangement shown in FIG. 1 requires four transistors and two control signals per column.
As also shown schematically in FIG. 2, the outputs from the transfer gates 72, 74, 76, 78 can be provided as pairs of inputs to a sense amplifier circuit 82 in order to detect a read data value during a read operation, whilst for a write operation write driver circuitry 84 can drive inputs to those transfer gates, causing an input at a logic one voltage level to be input to one transfer gate whilst a logic zero voltage level is input to the other transfer gate connected to the other bit line of the selected column.
The presentation entitled “Memory” by K Yun, UC San Diego, appearing on the Internet at the address http://paradise.ucsd.edu/class/ece165/notes/lecC.pdf gives a general overview of the operation of various memory cell designs, and on page 16 illustrates a column multiplexer arrangement in which the read path and write paths are maintained separately, but requiring three transistors per column. However, such an arrangement does not work in modern memories, as sense amplifiers are used to detect the values stored in the memory cells during the read operation, and this would require the addition of an extra read transistor into the design, hence again resulting in the requirement for four transistors per column.
The individual memory cells of the memory array can take a variety of forms. In one particular implementation, the memory cells may be SRAM memory cells, requiring a pair of bit lines to be connected to each memory cell. Such SRAM cells can be arranged in a variety of ways, FIG. 3 illustrating one particular example construction where a 6T SRAM memory cell is used to form each SRAM memory cell of an SRAM memory. As can be seen, the memory cell consists of two PMOS transistors 100, 110 and two NMOS transistors 120, 130. A node 140 is provided between the PMOS transistor 100 and the NMOS transistor 120, and similarly a node 150 is provided between the PMOS transistor 110 and the NMOS transistor 130. The bit line 180 is connected to the node 140 via an access transistor 160, and similarly the bit line 190 is connected to the node 150 via an access transistor 170.
Two different states can be stored within the memory cell shown in FIG. 3, a first state being where the node 140 is at a ground potential and the node 150 is at a power supply potential Vdd, and the second state being a state where the node 140 is at the power supply potential Vdd and the node 150 is at the ground potential.
There is an increasing demand for memory devices to be constructed which are smaller and consume less power than their predecessor designs, whilst retaining high performance. New technologies are being developed which allow a reduction in the size of the individual transistors making up each memory cell, and indeed the transistors making up the associated access control circuitry. However, as the memory cells decrease in size, the variation in behaviour between individual memory cells tends to increase, and this can adversely affect predictability of operation. One particular issue that arises is that as the size of the transistors decrease, they exhibit more leakage current. Hence, considering by way of example the SRAM cell shown in FIG. 3, the access transistors 160, 170 may exhibit more leakage onto the associated bit lines 180, 190. The effect of this is that the leakage will affect the maximum length of bit line which can be supported within the memory device whilst ensuring correct operation.
One way to seek to address this problem is to partition the column up into a plurality of separate sub-columns in the vertical direction, thus creating a plurality of sub-arrays in the bit line direction of the memory device. Each sub-array then needs to be provided with some local access control circuitry to enable data to be read from, and written to, the sub-array, with the various local access control circuits then being connected to a global 10 circuit responsible for outputting data from the memory device and receiving write data to be written into the memory device. Whilst the creation of such sub-arrays within the device reduces the size of the bit lines, and hence improves reliability of operation when using the reduced size transistors available using modern memory technologies, the size of the associated access control circuitry used to read from, and write to, those sub-arrays becomes a significant factor. In particular, each time the bit line length is reduced by a factor of two, the area required for the associated local access control circuitry will increase by a factor of two (assuming the memory device is still to have the same number of memory cells overall), due to the need to duplicate the local access control circuitry.
Accordingly, it would be desirable to develop a technique which enabled the size of the access control circuitry to be reduced, so as to reduce the effect that such access control circuitry has on the area efficiency of the memory device.